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SAFE4I - Sicherer Automatischer Entwurf für Industrieanlagen

Overview

Industrial manufacturing is being driven forward in many areas by Industry 4.0 and by the Internet of Things. In this context, corresponding standards for functional safety (safety), such as IEC 61511 and IEC EN 61508, require not only the safeguarding of the automation solution as a whole, but also the safeguarding of components and subsystems. The SAFE4I joint project, funded by the BMBF (German Federal Ministry of Education and Research), developed automation solutions for generating functionally safe software together with 15 other partners. The acceleration of the development of functionally safe software is to be achieved within the framework of SAFE4I by strictly separating the design of the required software functionality from the measures for software safeguarding.

To secure the software against hardware errors, such as memory defects or transmission errors in sensors, these must be mapped exactly in the hardware. The Schaltungstechnik group therefore implemented a low-energy IoT device as part of SAFE4I, which will be developed as a freely available open-source demonstrator platform. The low-energy IoT device consists of a RISC-V processor core with TX/RX and SPI communication interfaces. In addition, the processor is complemented by a wireless component that allows it to be activated by a wakeup signal.

The low-energy IoT device is synthesized from existing models at UC Berkeley and ETH Zurich for an Artix-7 FPGA and for CMOS chip fabrication using TSMC 65nm technology. The existing Verilog and SystemVerilog models will be complemented in the project with other partners by implementations in Verilog-A and SystemC-AMS to enable simulation of the entire system at multiple levels of abstraction. In addition to developing low-power hardware, the circuit engineering group is also working on researching efficient fault injection techniques and safety measures to ensure functional safety.

The RISC-V architecture was chosen as the platform because it has received worldwide acceptance in industry and research. Meanwhile, a wide range of RISC-V hardware models and software development tools are freely available.

Key Facts

Project duration:
10/2017 - 12/2021
Websites:
SAFE4I - Sicherer Automatischer Entwurf für Industrieanlagen
Projektwebsite

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Principal Investigators

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Bastian Koppelmann

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apl. Prof. Dr. Wolfgang Müller

System and Circuit Technology / Heinz Nixdorf Institut

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Prof. Dr.-Ing. J. Christoph Scheytt

System and Circuit Technology / Heinz Nixdorf Institut

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